1. Field of the Invention
This invention relates to the layout of electronic circuits and more particularly to complex computer aided design layout and placement of vias and via arrays in a design layout of, for example, an integrated circuit (IC) device or printed wiring board (PWB), where the design layout includes arbitrarily complex metal shapes.
2. Description of the Related Art
As computer chip manufacturers seek to pack ever more function into ever less space, design requirements have become more stringent. “Nanometer technology”—so-called because the minimum feature size is measured in nanometers—has become prevalent, bringing with it new design rules.
Among the new design rules are rules for metal enclosures for vias, that is, metal layer-to-metal layer connections, that call for differing amounts of metal enclosure outside the via depending on the location of the via relative to the metal path in which it resides. These rules are known as asymmetric metal enclosure design rules, and are a type of design for manufacturability (DFM) rule. Asymmetric metal enclosure rules require more metal enclosure at the metal path end, while allowing less metal enclosure at the metal path side. More metal enclosure at the path end guarantees that vias will be covered at the metal path end, while less metal enclosure at the metal side allows for straighter and narrower metal paths, which helps reduce the design size, and makes the design easier to fabricate. To profit from these advantages, use of asymmetric metal enclosures is encouraged in nanometer technology designs.